Group News and Media Coverage

March 15, 2024

Prof. Cosmi Lin received a research grant from the NASA On-Demand Manufacturing of Electronics (ODME) program. We will be working with NASA closely and develop new device fabrication and characterization technologies for 2D semiconductor field-effect transistors for radiation hardened microelectronics applications.

January 15, 2024

Our graduate student, Mr. Farhan Zahin, is awarded the Samsung Austin Semiconductor Fellowship. He will lead a team of four other undergraduate awardee, Mr. Matthew Cupich, Ms. Rachel Lee, Mr. Dhruv Nandwani, and Mr. Christian Schade, and work on a two-semester project about substitutional doping of 2D semiconductors. Congratuations!

Making low-resistance metal contacts to 2D materials is a bottleneck to their practical use in CMOS transistors. Progress has been made with n-type contacts for use with nFETs, but low-resistance p-type contacts for use with pFETs are more challenging because of the electro-thermodynamic conditions that arise between p-type metals and 2D materials. These conditions create an energy mismatch called the Schottky barrier: the greater the Schottky barrier height, the greater the resistance to current flow. In the paper #28.1, a TSMC-led team conducted computational modeling and simulation studies to investigate various materials for use as p-type contacts to the 2D material WSe2. As a result of these studies, they identified two new strategies as realistic pathways to achieving Schottky barrier-free (i.e., ohmic) low-resistance p-type contacts: van der Waals metallic contacts using a material like 1T-TiS2, and bulk semi metallic contacts using various materials, of which Co3Sn2S2 was identified as exceptionally good, with a theoretical contact resistance as low as 20 Ω·μm. Physical experiments were performed to further evaluate it.

Link: https://www.ieee.org/ns/periodicals/EDS/EDS-JANUARY-2023-HTML/index.html

Researchers at leading foundry TSMC are developing transistors with feature sizes below 1nm to scale chip designs even further and have shown the first nanosheet transistor with a gate all around (GAA) topology.

A TSMC-led team conducted computational computer modeling and simulation studies to investigate various materials for use as p-type contacts to the 2D material WSe2.

Link: https://www.eenewseurope.com/en/tsmc-heads-below-1nm-with-2d-transistors-at-iedm/

A paper co-authored by Berkeley EECS Prof. Jeffrey Bokor, his postdoc Yuxuan Lin, Berkeley Physics Prof. Alex Zettl, his postdoc Cong Su, and researchers at MIT, among others, describes a more efficient method of connecting atomically thin 2-D materials to other chip elements, making them a more promising alternative to 3-D silicon-based transistors.  

Link: https://eecs.berkeley.edu/news/2021/05/2-d-semiconductor-contact-resistances-approach-quantum-limit

Atomically thin materials are a promising alternative to silicon-based transistors; now researchers can connect them more efficiently to other chip elements.

Link: https://news.mit.edu/2021/2d-transistors-microchip-0513

Researchers at MIT reported a method of depositing different materials within a single chip layer, which could lead to more efficient computers. 

Link: http://news.mit.edu/2016/new-chip-fabrication-approach-0127