Low-Resistance p-Type Contacts to 2D Materials

IEEE Electron Device Society Newsletter, January 1, 2023

Making low-resistance metal contacts to 2D materials is a bottleneck to their practical use in CMOS transistors. Progress has been made with n-type contacts for use with nFETs, but low-resistance p-type contacts for use with pFETs are more challenging because of the electro-thermodynamic conditions that arise between p-type metals and 2D materials. These conditions create an energy mismatch called the Schottky barrier: the greater the Schottky barrier height, the greater the resistance to current flow. In the paper #28.1, a TSMC-led team conducted computational computer modeling and simulation studies to investigate various materials for use as p-type contacts to the 2D material WSe2. As a result of these studies, they identified two new strategies as realistic pathways to achieving Schottky barrier-free (i.e., ohmic) low-resistance p-type contacts: van der Waals metallic contacts using a material like 1T-TiS2, and bulk semi metallic contacts using various materials, of which Co3Sn2S2 was identified as exceptionally good, with a theoretical contact resistance as low as 20 Ω·μm. Physical experiments were performed to further evaluate it.


Semimetals make good p-type contacts

Nature Electronics, December 2, 2022

Two-dimensional semiconductors, such as molybdenum disulfide and tungsten diselenide, are potential replacements for silicon in the channels of ultra-scaled field-effect transistors. However, making good p-type contacts with these materials is challenging and often results in a high amount of metal-induced gap states and Fermi level pinning effects, and thus a high Schottky barrier. Semimetals such as bismuth have previously been shown to make good n-type contacts with two-dimensional semiconductors. Yuxuan Cosmi Lin, Han Wang and colleagues now show using computational models that bulk semimetallic contacts can also be used to achieve low-resistance p-type contacts.


TSMC heads below 1nm with 2D transistors at IEDM

EE News Europe, October 18, 2022

Researchers at leading foundry TSMC are developing transistors with feature sizes below 1nm to scale chip designs even further and have shown the first nanosheet transistor with a gate all around (GAA) topology.

A TSMC-led team conducted computational computer modeling and simulation studies to investigate various materials for use as p-type contacts to the 2D material WSe2.


2D transistor technology overcomes barrier to ever-shrinking computer chips

UC Berkeley College of Engineering, May 17, 2021

A new advance led by researchers at MIT, UC Berkeley and the Taiwan Semiconductor Manufacturing Company makes it viable to replace bulky silicon-based transistors with atomically thin 2D materials.


2-D semiconductor contact resistances approach the quantum limit

UC Berkeley EECS Department, May 14, 2021

A paper co-authored by Berkeley EECS Prof. Jeffrey Bokor, his postdoc Yuxuan Lin, Berkeley Physics Prof. Alex Zettl, his postdoc Cong Su, and researchers at MIT, among others, describes a more efficient method of connecting atomically thin 2-D materials to other chip elements, making them a more promising alternative to 3-D silicon-based transistors.  


挑戰物理極限 延續摩爾定律 臺大攜手台積電、美國麻省理工學院跨國研究登Nature

National Taiwan University, May 14, 2021



Advance may enable “2D” transistors for tinier microchip components

MIT News, May 13, 2021

Atomically thin materials are a promising alternative to silicon-based transistors; now researchers can connect them more efficiently to other chip elements.


The Superpowers of Super-Thin Materials

In materials science, 2-D is the new 3-D.

The New York Times, January 7, 2020

New York Times reporter Amos Zeeberg spotlights how Prof. Tomás Palacios and his research group are developing super-thin, 2-D materials that could help power the internet of things. “What if we were able to embed electronics in absolutely everything,” says Palacios of the inspiration for his group’s work. 


New chip fabrication approach

MIT News, January 27, 2016

Researchers at MIT reported a method of depositing different materials within a single chip layer, which could lead to more efficient computers.